Samsung and SK hynix Target Robot DRAM as Demand Multiplies
Average memory per humanoid will more than double to 39 gigabytes by 2030, shifting packaging requirements toward low-power LPDDR and specialized 3D NAND architectures.
Counterpoint Research reported Oct. 11, 2026 that global DRAM demand for humanoid robot computing systems will jump more than 20-fold to roughly 172,000 terabits by 2030.
The research firm estimated baseline consumption at 8,300 terabits for 2026. The projected surge reflects accelerating deployment of physical artificial intelligence across industrial manufacturing and logistics facilities worldwide.
Average dynamic random-access memory per humanoid unit will expand from 19 gigabytes in 2026 to 39 gigabytes in 2030, the report said. That constitutes more than a twofold increase in onboard memory density.
Humanoid machines require dedicated memory to process high-volume sensor streams in real time. Systems must synthesize visual feeds from cameras, spatial depth from light detection and ranging sensors, and tactile pressure from mechanical joints.
The architectural transition toward end-to-end neural networks and world models increases compute density. World models predict physical environmental changes, requiring low-latency memory to maintain stable autonomous locomotion.
The transition presents an expanding commercial target for Samsung Electronics and SK hynix. Together, the two South Korean semiconductor manufacturers account for roughly 70% of global dynamic random-access memory production capacity.
Unlike hyperscale data centers that run on power-intensive high-bandwidth memory, humanoid robots face strict battery constraints. Mobile power packs cannot easily support the thermal and energy loads of conventional server architectures.
Robot manufacturers are instead prioritizing low-power double data rate chips and high-capacity flash storage. Chipmakers are designing specialized packages that balance data bandwidth against constrained electrical power envelopes.
Over the longer horizon, the report identified three-dimensional DRAM as the critical memory architecture for compact robotic heads. Vertical stacking allows designers to multiply capacity without enlarging circuit footprint inside tight mechanical enclosures.
SK hynix demonstrated its physical AI hardware trajectory during the Nvidia GTC gathering on March 20, 2026. The chipmaker unveiled 128-gigabyte low-power DDR5X modules and small-outline compression attached memory modules designed for robotics computing platforms.
The specialized modules connect to Nvidia Jetson and Thor processing boards, SK hynix said. The design lowers active operating power while delivering the transfer rates required for continuous visual perception and motor actuation.
SK hynix also exhibited SOCAMM2 units alongside next-generation server memory at the Future of Memory and Storage conference on Aug. 7, 2026. The firm pointed to mobile AI packaging as a distinct product track from vertical server stacks.
Samsung Electronics outlined its competing hardware roadmap on Aug. 4, 2026 during the Future of Memory and Storage conference. Executive Vice President Jin-Yub Lee presented mockups of specialized three-dimensional memory structures engineered for on-device robotic intelligence.
Samsung introduced concept models for zHBM and zNAND-O at the conference. The zHBM architecture stacks memory dies directly atop host processors, cutting physical interconnect distance and reducing overall power draw.
The company also presented zNAND-O, an on-device flash module that bridges the latency gap between standard flash and system memory. Samsung said the design achieves read latency below three microseconds to support continuous model execution.
To support high-density storage, Samsung revealed its tenth-generation V-NAND with more than 400 layers using wafer bonding technology. The package boosts areal storage density by 58% compared to previous production generations.
Samsung also created an internal Robotics eXperience Business Division under its chief executive officer in July 2026. The division coordinates semiconductor packaging, actuator hardware and system software for commercial humanoid prototypes.
Competitors are pursuing comparable mobile memory targets. Micron Technology Chief Executive Officer Sanjay Mehrotra said on Sept. 30 that advanced autonomous machines require over 200 gigabytes of memory and several terabytes of storage.
The companies have not published any joint supply agreements or filed regulatory disclosures on the Korea Exchange confirming market speculation of a shared humanoid memory supply alliance.
Original equipment manufacturers will showcase second-generation humanoid prototypes at the Consumer Electronics Show in Las Vegas on Jan. 5, 2027. Commercial mass deployment schedules remain scheduled across 2027 and 2028.
Impact map
How this development propagates across the region and out to global buyers.
| Event | Korea | China | Japan | Global impact |
|---|---|---|---|---|
| Humanoid memory expansion | Samsung and SK hynix shift low-power LPDDR and 3D NAND lines to physical AI | Unitree and UBTech test low-power DRAM modules to bypass server-chip export rules | Component suppliers adjust sensor interfaces for LPDDR5X and SOCAMM2 standards | Average humanoid DRAM BOM content doubles to 39GB as world models enter production |
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- Nvidia locks up 37% of global HBM supply for AI accelerators Also on Micron Technology, Nvidia, SK hynix
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Confidence: medium — how we grade this
The documents behind this briefing are linked above. East Asia Brief produces its English text with AI assistance under human editorial review, and does not translate or republish other outlets' articles. See our methodology and AI policy. Spotted an error? Tell us.
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