Micron taps TSMC for custom HBM4E memory, taking on SK hynix

Micron Technology detailed plans on Oct. 2 to outsource custom HBM4E base dies to Taiwan Semiconductor Manufacturing Co., directly challenging SK hynix's dominant grip on Nvidia's artificial intelligence accelerator contracts.

The co-designed architecture, designated NVHBM, targets up to 30% higher bandwidth and roughly 15% lower power consumption than standard HBM4E memory stacks by embedding custom memory controllers directly into the base logic die.

The custom layout shrinks the physical input-output interface package area by up to 67%. That reduction frees silicon surface area on Nvidia's next-generation graphics processing units and open NVLink Fusion infrastructure platforms.

Micron has collaborated with Nvidia for more than a year to engineer the custom architecture, Scott DeBoer, president and chief technology and products officer at Micron, said during the product briefing.

The development represents a strategic shift from Micron's fifth-generation HBM4 design, DeBoer said. That earlier generation relied on an internal base die manufactured across Micron's proprietary memory fabrication lines.

Micron is adopting foundry manufacturing for both its custom NVHBM line and its standard JEDEC-compliant HBM4E product family. The dual track ensures broader compatibility across hyperscale cloud customer requirements.

Micron will fabricate the core DRAM layers for the HBM4E stacks using its sixth-generation 10-nanometer-class 1-gamma manufacturing process. TSMC will manufacture the underlying base logic dies using its advanced logic lines.

The outsourced base dies will use TSMC's 3-nanometer-class logic process. The advanced node offers measurable operational improvements in power, performance and silicon area over legacy DRAM-based logic wafers.

SK hynix supplies more than 50% of the global high-bandwidth memory market. The South Korean manufacturer previously formed a dedicated alliance with TSMC to fabricate base dies for its own custom HBM4 products.

Micron's entry into TSMC's fabrication queue ends SK hynix's exclusive position as the sole memory maker tapping Taiwan's pure-play foundry network for next-generation custom artificial intelligence hardware.

Outsourcing base die fabrication will not erode corporate gross margins, Manish Bhatia, chief operating officer at Micron, said. Customized memory architectures command higher average selling prices and superior investment returns, Bhatia said.

Micron has already committed most of its 2027 high-bandwidth memory production volume under commercial agreements, Chief Executive Sanjay Mehrotra said. Strong enterprise demand has kept production lines fully allocated through future quarters.

The company has signed 26 new or extended supply customer agreements, Mehrotra said. These take-or-pay contracts require buyers to fund committed capacity regardless of whether they take immediate physical delivery.

More than 35% of Micron's projected operational revenue through 2030 is now secured under these long-term commitments. The contractual structure shields memory investments from traditional cyclical swings in commodity pricing.

Micron's HBM4 production ramp is progressing roughly twice as fast as its prior 12-high HBM3E manufacturing cycle, DeBoer said. Yield optimization on the newest memory stacks has advanced without major operational disruptions.

Conventional memory architecture places the external memory controller directly on the host processor silicon. That design consumes critical die area that accelerator developers prefer to reserve for arithmetic compute engines.

Integrating the controller directly into TSMC's base die shortens electrical interconnect wiring between memory stacks and processors. The shortened paths reduce thermal resistance across high-density artificial intelligence server racks.

The architectural shift increases manufacturing dependence on TSMC's advanced packaging lines. Nvidia, Apple and specialized accelerator designers already compete for TSMC's finite chip-on-wafer-on-substrate packaging allocations in Taiwan.

Samsung Electronics continues to rely on an integrated device manufacturing model, fabricating both core memory layers and base logic dies in-house. However, Samsung has faced prolonged qualification cycles for advanced graphics processors.

Samsung and SK hynix categorize their competing sixth-generation 10-nanometer-class DRAM as 1c nodes. Those nodes compete directly against the electrical efficiency and cell density of Micron's 1-gamma core DRAM dies.

The shift toward tailored base dies transforms high-bandwidth memory from an interchangeable component into proprietary sub-assemblies. Memory suppliers must now adapt circuitry to host architectures defined by individual accelerator designers.

Competition among memory makers is expanding beyond cleanroom DRAM stacking into advanced logic design and foundry collaboration. Packaging yield and logic integration now dictate supply allocations for artificial intelligence hardware.

The companies have not published a joint contractual filing, and TSMC has not issued a standalone confirmation specifying foundry allocation volumes or wafer pricing terms for the project.

Micron schedules full-scale commercial volume production of the custom NVHBM modules for 2027. That timeline aligns with Nvidia's planned deployment schedule for next-generation NVLink Fusion computing infrastructure.