TSMC Reaffirms 2028 Target for 1.4nm Chips at Taichung Fab

Taiwan Semiconductor Manufacturing Co. maintained its 2028 target for commercial 1.4-nanometer chip production on Sept. 11, 2026, pushing back on market speculation that fabrication lines would start commercial output next spring.

The clarification followed reports that the foundry had accelerated mass production of its A14 node by a full year to April 2027. Those reports mischaracterized local construction milestones as finished semiconductor manufacturing.

The Taichung Fab 25 complex represents an estimated NT$1.2 trillion ($37.5 billion) investment across four phases. Once all four plants operate, the facility will generate over NT$500 billion ($15.6 billion) in annual revenue.

The accelerated timeline originated in an administrative briefing on Sept. 9 by the Central Taiwan Science Park Administration. Deputy Director General Wang Chun-chieh briefed reporters on structural progress at the park's Phase 2 expansion.

Crews have finished the steel skeleton for Fab 25 Phase 1 and are now pouring floor slabs, Wang said. Civil building completion moved forward by roughly six months to April 2027 for cleanroom fit-out and trial operations.

Foundation work is progressing on the adjacent Phase 2 building, which remains scheduled for structural completion in October 2027, Wang said. The combined four-plant complex will eventually support 4,500 manufacturing jobs in central Taiwan.

Civil building handover does not equal commercial wafer delivery in advanced lithography. Foundries require 12 to 18 months after building completion to install extreme ultraviolet tools, calibrate vacuum chambers and stabilize wafer yields before accepting customer orders.

TSMC reiterated its node roadmap during its second-quarter earnings briefing on July 16, 2026. The company confirmed that its 1.4-nanometer A14 node will enter risk production in 2027, with volume production scheduled for 2028.

Successive process refinements, designated A13 and A12, will follow in 2029, according to TSMC investor filings. Those future iterations will integrate second-generation nanosheet gate designs and backside power delivery networks.

Compared to the 2-nanometer N2 node entering volume lines, A14 delivers a 10% to 15% speed increase at identical power levels. The process also offers a 25% to 30% reduction in power consumption at identical operating frequencies.

The A14 node also increases logic transistor density by roughly 20%, TSMC said. That density gain allows chip designers to pack more execution units into artificial intelligence processors without expanding the physical die area.

Shifting fabrication dates would alter capital procurement for Apple and Nvidia, TSMC's two largest customers. Together, those two American designers account for more than 35% of TSMC's annual wafer revenues.

Hyperscalers and fabless designers plan design tape-outs two to three years before planned device debuts, industry analysts said. Mask production and physical design rules prevent system builders from advancing silicon rollouts by an entire year on short notice.

Advanced packaging facilities in the same industrial park will integrate future 1.4-nanometer silicon. TSMC is building its AP5B advanced packaging line nearby to bond logic compute tiles directly with high-bandwidth memory for next-generation data centers.

Tool vendors also operate on rigid multi-year production schedules. ASML Holding and Tokyo Electron configure extreme ultraviolet lithography systems years in advance, making sudden one-year shifts in foundry production lines technically improbable.

The pace of advanced fab construction directly affects Intel and Samsung Electronics. Both competitors are pouring billions of dollars into sub-2-nanometer fabrication lines in an attempt to challenge TSMC's dominance in contract manufacturing.

Intel has staked its foundry turnaround on its 14A process node, targeting external customer wafer runs starting in 2027. Any true acceleration by TSMC would squeeze Intel's chances of winning commitments from American cloud providers.

Samsung Electronics is developing its SF1.4 node for commercial release in 2027. However, Samsung commands less than 10% of global leading-edge foundry capacity, leaving the South Korean chipmaker vulnerable to TSMC's massive manufacturing scale.

The Central Taiwan Science Park Administration expects Fab 25 Phase 1 tool installation to begin in April 2027, with Phase 2 structural completion following in October 2027. Construction permit reviews for Phase 3 and Phase 4 will continue through late 2027.

TSMC has not published commercial wafer pricing schedules for the A14 node, and the company has not filed regulatory disclosures indicating early customer tape-outs. Management has not revised its official commercial production calendar.