TSMC sees 3nm revenue overtake 5nm node on surge in AI accelerators

Taiwan Semiconductor Manufacturing Company will lift quarterly three-nanometer wafer revenue above NT$400 billion in the third quarter of 2026, surpassing its five-nanometer node as reported Sept. 7.

The projected output value equals $12.7 billion and represents more than 30% of total company sales. Market projections published Sept. 7 by Taiwan media and TrendForce point to record shipments.

TSMC narrowed the revenue gap between the two advanced nodes during the spring. Its five-nanometer family contributed 33% of wafer revenue in the second quarter, down from previous highs.

Three-nanometer chips accounted for 30% of sales in the same period. That represented a five-percentage-point increase from 25% in the first quarter of 2026, according to company financial disclosures.

The foundry operator reported consolidated revenue of NT$1.27 trillion ($40.20 billion) for the April-June quarter on July 16. Net income reached a record NT$706.56 billion ($22.36 billion) during that period.

Management set third-quarter revenue guidance between $44.6 billion and $45.8 billion during its July 16 conference. The outlook assumed an exchange rate of 32.0 New Taiwan dollars per US dollar.

Surging demand for artificial intelligence hardware is driving the transition to smaller circuit geometry. Global semiconductor designers are transferring their highest-performance processing units to the three-nanometer production lines.

Nvidia is ramping commercial production of its Rubin computing architecture on TSMC lines. That move follows extensive wafer allocations for Blackwell processors that occupied advanced packaging capacity throughout early 2026.

Advanced Micro Devices and Broadcom have expanded their manufacturing commitments for computing silicon. Both designers rely on TSMC advanced fabrication to produce accelerators for hyperscale data center operators.

Consumer electronics customers are adding seasonal pressure to fab utilization. Apple and Qualcomm have reserved large wafer lots for smartphone application processors scheduled to enter retail hardware this autumn.

TSMC plans to raise monthly three-nanometer wafer starts to 180,000 units in early October, brokerage Wedbush estimated. That volume marks an increase from 150,000 monthly wafer starts in the first half.

Production capacity for the three-nanometer family remains constrained despite equipment installations. The manufacturer has converted select five-nanometer production tooling to relieve bottlenecks across its domestic semiconductor fabrication plants.

The company is adding domestic manufacturing space to support long-term volume requirements. TSMC plans to open an additional three-nanometer plant at the Southern Taiwan Science Park in Tainan during the first half of 2027.

Overseas expansion is progressing along identical technology tiers. The second manufacturing plant at TSMC Arizona site in Phoenix will adopt three-nanometer process technology, with volume output scheduled for the second half of 2027.

TSMC estimates combined monthly capacity for two-nanometer and three-nanometer wafers will exceed 400,000 units by 2028. That projection combines official corporate roadmaps with industry capacity data.

The company raised its full-year 2026 capital budget to between $60 billion and $64 billion on July 16. The revised capital plan increased from an initial target of $52 billion to $56 billion announced in January.

TSMC maintains an effective monopoly over sub-five-nanometer contract manufacturing. Rival foundry operators have failed to secure commercial production orders from major artificial intelligence hardware developers.

Samsung Electronics continues to struggle with production yields on its gate-all-around three-nanometer lines. The South Korean manufacturer has not won major external foundry contracts for premier artificial intelligence accelerators.

Intel has separated its foundry business into an independent operating subsidiary amid corporate restructuring. The American producer remains focused on cost reduction rather than competing for external leading-edge volume.

The absence of alternative contract manufacturers reinforces TSMC pricing power over fabless customers. Chip designers must accept elevated wafer prices to secure guaranteed volume allocations for upcoming product generations.

Premium manufacturing fees support corporate profitability. TSMC delivered a gross margin of 67.7% in the second quarter and guided third-quarter gross margin within a band of 65.0% to 67.0%.

Next-generation production is beginning to contribute to financial results. Two-nanometer process technology generated 3% of wafer sales in the second quarter, marking its first commercial revenue entry.

The node will scale in parallel with three-nanometer output as customers prepare subsequent architectural upgrades. TSMC noted that initial device performance and memory test yields on advanced test chips remain ahead of schedule.

The foundry will report audited third-quarter results and node revenue shares during its mid-October 2026 investor conference. Until that earnings disclosure, node totals remain industry estimates.