Synopsys certifies TSMC A14 EDA flows and tapes out 64G UCIe

Synopsys completed electronic design automation certification for TSMC's 1.4-nanometer A14 process on Sept. 28, 2026, advancing tape-outs of 64-gigabit-per-second Universal Chiplet Interconnect Express IP across cutting-edge silicon nodes.

The certification validates digital and analog design suites for TSMC, which commands more than 60% of global foundry revenue. It allows semiconductor engineers to construct physical layouts for angstrom-era manufacturing.

The 64-gigabit-per-second die-to-die interface — an open standard connecting separate silicon dies inside a package — doubles the throughput of previous 32-gigabit standards. It provides interconnect density required for multi-die packages that exceed reticle limits.

Synopsys said its certified design flow covers logic synthesis through physical timing signoff. Both companies are also developing automated analog device-routing technology to reduce engineering hours spent manually drawing transistor layouts.

The 64G chiplet IP completed test tape-outs on TSMC's 2-nanometer and 3-nanometer fabrication lines. The silicon designs integrate embedded design-for-test capabilities to diagnose interconnect failures within enclosed packages, the vendor said.

Hardware validation had cleared previous milestones on TSMC's enhanced 3-nanometer N3P node. Synopsys operated UCIe-A test circuits at 40 gigabits per second across CoWoS-S silicon interposers to verify signal margins.

Development milestones also expanded across TSMC's backside-power N2P node. Synopsys reached tape-out readiness on N2P for high-bandwidth memory HBM4 interfaces, PCIe 7.0 transport controllers and 224-gigabit-per-second Ethernet physical layers.

The N2P enablement package contains low-power double data rate LPDDR6 controllers, one-time programmable memory and silicon lifecycle sensors. These on-chip sensors track process, voltage and temperature variations during high-load computing workloads.

The HBM4 interface IP targets next-generation artificial intelligence accelerators that require 2,048-bit bus widths. That bus width doubles the interconnect channel size of current HBM3E memory stacks, improving throughput.

Both companies integrated agentic artificial intelligence into their software stack to manage escalating physical complexity. Synopsys Custom Compiler uses autonomous algorithms to migrate analog circuit blocks across process generations without manual redesigns.

Synopsys Fusion Compiler now incorporates large language models to optimize logic timing and cell placement. Meanwhile, the 3DIC Compiler platform automates floorplanning across multiple dies integrated on TSMC's 3DFabric packaging formats.

Chiplet layout requires balancing interconnect length, thermal dissipation and mechanical stress across heterogeneous silicon slabs. Automated floorplanning resolves multivariable routing conflicts before engineers submit final database files to the foundry, Synopsys said.

Advanced packaging tools also added simulation models for integrated voltage regulators on CoWoS substrates. Direct power delivery stabilizes high-current transients as hyperscale accelerators approach thermal design thresholds above 1,000 watts.

The collaboration also covers electronic-photonic co-design for TSMC's Compact Universal Photonic Engine, known as COUPE. The toolset allows engineers to verify optical waveguide routes and high-speed electrical driver circuits simultaneously.

EDA rival Cadence Design Systems also announced A14 flow certifications and Universal Accelerator Link IP validation on TSMC nodes during the forum. Siemens certified its Calibre verification toolchain for the same geometry.

The triad of design software vendors ensures fabless designers face standard software interfaces across TSMC's advanced nodes. That uniformity helps cloud operators plan processor roadmaps across multiple generations of silicon.

Nvidia relies on TSMC for 100% of its advanced data center graphics processing units, which generate roughly 85% of its quarterly revenue. The chipmaker requires certified multi-die flows to integrate future accelerator architectures.

Advanced Micro Devices similarly sources 100% of its high-performance Instinct server chips from TSMC foundries. The multi-die packaging workflows directly influence how AMD partitions compute chiplets and memory across carrier substrates.

South Korea's SK hynix, which controls more than 50% of the high-bandwidth memory market, is shifting HBM4 base dies from memory processes to advanced foundry logic. The change ties memory suppliers directly to TSMC packaging ecosystems.

Samsung Electronics is preparing its own 4-nanometer logic process for HBM4 base dies. However, customers demanding TSMC CoWoS packaging require memory architectures verified against TSMC foundry design kits and Synopsys controller IP.

Developing a custom processor on 2-nanometer silicon exceeds $500 million in design and mask expenses. Early electronic design automation certification reduces tape-out failure risks for fabless firms committing capital to cutting-edge nodes.

Synopsys and Cadence control roughly 70% of the worldwide electronic design automation market. Mutual qualification with TSMC locks high-performance compute clients into their respective synthesis, simulation and signoff toolchains.

The companies did not disclose commercial customer tape-out schedules or defect-density yield targets for the A14 process.

TSMC plans to begin volume production of its baseline 2-nanometer N2 node in late 2025, followed by the commercial introduction of A14 in 2027.