Rapidus holds 2nm chip timeline as 17 partners join network
The Japanese venture keeps its 2027 mass-production goal while enlisting Cadence and Synopsys to lower design barriers against…
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All companies →Cadence Design Systems
Every EAB briefing that touches Cadence Design Systems — capital spending, plants, M&A, earnings and policy exposure. 4 briefings.
- First seen
- September 28, 2026
- Latest
- October 9, 2026
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Rapidus forms 17-firm design alliance to back 2nm chip ramp
The Japanese foundry partnered with Synopsys, Cadence and domestic design houses to build an IP library and reduce client…
Synopsys expands TSMC pact with agentic AI chip design tools for A14
The deployment validates autonomous EDA workflows across TSMC's 1.4-nanometer A14 node, multi-die CoWoS interposers and HBM4…
Synopsys certifies TSMC A14 EDA flows and tapes out 64G UCIe
The milestone expands 2-nanometer IP libraries for HBM4 memory and CoWoS packaging, locking fabless chipmakers into angstrom-era…