DeepSeek cuts AI memory use 75%, rattling global chipmakers

DeepSeek shook global memory suppliers on Sept. 12, 2026, as trading desks weighed its new artificial intelligence model that cuts high-bandwidth memory requirements by 75% during inference.

The Chinese developer released DeepSeek-V4.1-Flash, an open-weight artificial intelligence architecture that compresses operational memory loads. The model slashes high-bandwidth memory (HBM) usage to one-fourth of the volume required by its predecessor, DeepSeek said.

South Korea's SK hynix and Samsung Electronics, which supply more than 90% of global high-bandwidth memory modules, faced immediate investor scrutiny. Market desks questioned whether algorithmic optimization would erode premium memory pricing power.

The technical breakthrough centers on key-value cache compression — the temporary working memory that stores conversational context during text generation. DeepSeek compressed that footprint to 890 bytes per token, down from earlier multi-kilobyte standards.

That 890-byte footprint represents a 437-fold memory reduction compared to the developer's first-generation model launched in 2023. The architecture also reduces auxiliary solid-state drive storage requirements by 87.5% through bounded replay caching techniques.

Equity markets reacted swiftly across East Asian trading hubs following the release. Shares of Samsung Electronics fell between 2.0% and 3.5% across two trading sessions, while SK hynix dropped between 2.2% and 3.0% in Seoul.

Selling pressure spilled over into Western markets as institutional investors trimmed semiconductor allocations. In New York, American depositary receipts of SK hynix and shares of Micron Technology both dropped more than 5% intraday.

DeepSeek-V4.1-Flash operates on a 552-billion parameter Mixture-of-Experts framework. Under this system, distinct sub-networks activate only for specialized tasks, avoiding the computational drag of running an entire deep neural network continuously.

The model introduces an asymmetric Causal Encoder-Decoder design to minimize active processing weights. The architecture activates 8 billion parameters during the input prompt phase and expands to 16 billion parameters during token output generation.

By throttling active parameters, the model processes large input contexts with minimal hardware contention. Data center operators can host larger user volumes on single server nodes without purchasing additional high-speed accelerator memory.

Commercial deployment began immediately on the developer's proprietary cloud infrastructure. DeepSeek adjusted its commercial application programming interface pricing schedule at 04:00 UTC on Sept. 10, passing memory efficiency gains to software developers.

Under the updated schedule, input tokens that hit pre-cached memory cost $0.006 per million tokens during peak hours. The rate drops to $0.003 per million tokens during off-peak windows, setting aggressive industry cost benchmarks.

The pricing compression carries direct commercial consequences for Korean memory producers. SK hynix derives roughly a third of its dynamic random-access memory revenue from high-bandwidth memory chips sold to major accelerator vendors.

Samsung Electronics has spent substantial capital expenditure expanding packaging capacity for 12-layer HBM3E products. A deceleration in inference memory intensity could compress gross margins on custom stacked memory lines entering volume fabrication.

For cloud hyperscalers, the demonstration provides leverage in long-term supply negotiations. Server operators facing tight capital budgets may delay planned memory upgrades if software optimizations double the throughput of existing hardware racks.

The architectural shift does not eliminate baseline semiconductor demand across data center facilities. Foundational model pre-training still requires full parameter visibility across distributed clusters, preserving core demand for high-density accelerator packages.

The practical consequence lands instead on the operational economics of inference clusters. As models transition from training runs to enterprise deployment, memory intensity per query determines the aggregate capital cost of AI services.

The efficiency gain may redirect procurement budgets toward alternative memory architectures. Enterprise data centers could deploy more low-power DRAM and Compute Express Link memory pools to handle workloads that no longer require peak HBM bandwidth.

Storage suppliers also face adjustments as persistent cache requirements shrink. DeepSeek's 87.5% cut in solid-state drive caching reduces the volume of enterprise flash memory needed to maintain session states across long context windows.

Western cloud infrastructure operators have not signaled any immediate cancellation of hardware contracts. Nvidia accelerator systems configured with maximum HBM allocations remain standard equipment across Tier-1 data center installations in North America.

The notice does not state whether total infrastructure-level memory procurement will fall, and DeepSeek has not published enterprise cluster deployment volumes or third-party server contract data.

Hardware roadmaps at proprietary silicon ventures could also adapt to the new framework. Application-specific accelerators designed with standard memory interfaces may compete more effectively against costly HBM-reliant accelerators in production inference tasks.

Starting at 04:00 UTC on Sept. 14, 2026, DeepSeek will route all legacy V4-Pro enterprise API traffic to DeepSeek-V4.1-Flash. The mandatory cutover binds commercial user workloads to the compressed memory format.

South Korean memory producers are scheduled to report third-quarter earnings in late October. Those disclosures will provide the earliest formal accounting of customer order adjustments and 2027 advanced packaging capital commitments.