CXMT plans 4F² server DRAM launch, hitting memory shares

Global memory chipmakers saw their shares slide on Oct. 12, 2026, after China's ChangXin Memory Technologies detailed plans to launch high-density 4F² server dynamic random-access memory by year-end.

The new architecture cuts individual memory cell area by 33% compared to standard 6F² designs. That structural reduction increases storage density by 30% to 50% across the silicon wafer, according to technical disclosures.

Micron Technology shares dropped 4.2% during trading, while SK hynix fell 4.5% and Samsung Electronics dropped 4.4%. The three incumbent manufacturers together controlled 87.6% of the global DRAM revenue pool in the second quarter.

ChangXin Memory Technologies, known as CXMT, revealed the product roadmap at the 4th Integrated Circuit and Chiplet Conference in Shanghai. CXMT President Cao Kanyu announced the server-memory schedule during a keynote presentation.

CXMT aims to deliver registered dual in-line memory modules — server cards known as DDR5 RDIMMs — using the architecture before Dec. 31. The modules buffer data commands between processors and memory.

DRAM cells store electrical charge to record digital bits. Standard industry cells use a 6F² layout, where the cell area equals six times the square of the minimum feature size printed on the silicon.

The 4F² layout packs cells into four squares of that minimum dimension. CXMT achieved the density gain by adopting vertical surrounded-gate transistors, which run channels upright instead of lying flat across the substrate.

The design also separates the memory cell array from peripheral control circuits across different wafers. Technicians connect the two layers using wafer-level hybrid bonding — direct copper-to-copper interconnection — to maintain electrical transmission speeds.

CXMT holds more than 300 published patent families covering vertical transistors and 4F² cell integration, Cao said. The company published its initial research on 4F² structures in 2021 before filing subsequent updates.

The Chinese memory producer captured 9.5% of global DRAM revenue in the second quarter of 2026, according to TrendForce data. That marked a rise from 7.6% in the first quarter of the year.

Samsung retained the top market position with a 39.4% revenue share in the same period. SK hynix held 24.9% of global DRAM sales, while US rival Micron accounted for 23.3%.

The disclosure followed a separate milestone announced on Sept. 20. CXMT opened volume manufacturing for its fifth-generation G5 platform, producing 24-gigabit low-power DDR5X chips built on an 11.95-nanometer half-pitch design rule.

US export controls prohibit shipments of extreme ultraviolet lithography scanners and advanced deposition tools to Chinese wafer fabs. CXMT has relied on deep ultraviolet lithography combined with architectural restructuring to achieve finer memory density.

The year-end delivery goal places CXMT roughly two years ahead of South Korean competitors on cell geometry. Samsung and SK hynix have targeted commercial introduction of 4F² memory structures around 2028.

Enterprise servers consume high-density DDR5 modules to feed cloud workloads and local artificial intelligence training clusters. Commodity DRAM pricing faces pressure if Chinese hyperscalers shift procurement away from foreign vendors to CXMT server products.

Chinese cloud providers such as Alibaba and Tencent represent major buyers of standard server memory. Diverting domestic server orders to CXMT would force global suppliers to compete harder for North American and European accounts.

The conference presentation does not state production yield rates or planned monthly wafer starts for the modules. CXMT has also not published validation results with tier-one server processor makers like Intel or AMD.

Industry analysts debate whether the year-end batch represents full commercial production or transitional engineering samples. Fabricating vertical channel transistors requires precise etching tools that remain under multilateral export licensing scrutiny by Western governments.

Chinese memory firms have used novel architectures to circumvent tool curbs before. Yangtze Memory Technologies previously commercialized Xtacking architecture for NAND flash, separating memory arrays from peripheral logic to reach competitive tier heights.

CXMT has also begun sampling high-bandwidth memory modules for domestic artificial intelligence accelerator makers. Local processor developers including Cambricon have evaluated early CXMT memory dies alongside specialized interposers, industry records show.

Market participants will track whether CXMT delivers functional DDR5 RDIMM samples to enterprise data centers by Dec. 31. Independent qualification cycles typically require three to six months before volume installation begins.