TSMC plans to lift wafer foundry prices by 3% to 6% from 2027

Taiwan Semiconductor Manufacturing Co. moved to raise wafer foundry prices by 3% to 6% on Sept. 28, 2026, targeting leading-edge fabrication nodes scheduled for delivery in January 2027.

The price adjustment applies across manufacturing lines but concentrates the heaviest increases on 2-nanometer and 3-nanometer processes. TSMC holds more than 60% of global foundry capacity and over 90% of advanced node production.

Fab capacity for sub-45-nanometer chips remains fully booked, while 8-inch fabrication plants operate above 100% capacity utilization. Customer order visibility now extends through 2030, according to supply chain sources.

Higher production expenses at overseas sites prompted the pricing review. Construction costs at TSMC fab projects in Arizona run four to five times higher than comparable facilities in Taiwan, raising structural operating costs.

Initial production ramp of 2-nanometer lines will dilute gross margin by three to four percentage points, the company said earlier. Overseas facilities add another two to three percentage points of margin drag over several years.

The pricing moves land directly on leading fabless customers with limited manufacturing alternatives. Apple and Nvidia depend on TSMC for all commercial shipments of their newest mobile application processors and artificial intelligence accelerators.

Nvidia, which commands roughly 80% of the AI graphics processor market, absorbs the cost first before passing it to cloud providers. Advanced packaging bottlenecks compound the financial impact for AI hardware vendors.

Shortages persist for CoWoS — chip-on-wafer-on-substrate packaging that mounts memory stacks alongside logic dies. TSMC has doubled packaging capacity annually, yet supply remains short of hyperscaler delivery targets.

Advanced Micro Devices, Qualcomm and MediaTek also face revised wafer-out contracts. Wafer-out marks the stage where completed silicon disks clear testing and leave the cleanroom for packaging and assembly.

Hyperscalers developing in-house custom silicon absorb similar foundry adjustments. Alphabet and Amazon Web Services rely on TSMC for application-specific integrated circuits designed to offload data center inference workloads.

The price adjustments extend beyond advanced logic into mature and specialty nodes. High AI accelerator volume requires auxiliary chips, including power management integrated circuits and microcontrollers produced on older lines.

TSMC negotiates mature and specialty process prices individually with each client based on order volume and fab allocation. Eight-inch wafer lines remain constrained by demand for analog chips and driver integrated circuits.

Taiwanese foundry peers have already signaled parallel pricing strategies. United Microelectronics Corp., Powerchip Semiconductor Manufacturing Corp. and Vanguard International Semiconductor began lifting quotes in 2026, with higher rates continuing into 2027.

Samsung Electronics and Intel Foundry face direct competitive fallout. Samsung maintains second-source capacity for select mobile clients, but leading AI hardware developers remain reluctant to shift core accelerator contracts away from TSMC.

High switching costs shield the foundry from client defection during price increases. Porting a complex chip design to another foundry requires up to two years of re-engineering and tens of millions of dollars in design and mask costs.

Upstream raw material suppliers also plan higher rates for 2027 deliveries. Long-term agreements for 12-inch epitaxial silicon wafers are negotiating increases between 15% and 25%, according to industry data.

Global silicon wafer shipments rose 7.4% year over year in the second quarter of 2026 to 3,573 million square inches, according to industry group SEMI. Rising substrate costs amplify the price pressure on finished wafers.

Fabless chip designers must decide how much of the foundry increase to pass to downstream server assemblers. Higher wafer quotes will begin affecting component bills of materials in the first quarter of 2027.

Physical chip shipments produced under the higher wafer rates will reach system makers by the second and third quarters of 2027. Finished server prices will reflect the accumulated foundry, substrate and packaging increases.

The notice does not state whether volume discounts will apply to long-term commitments, and the foundry has not released an official price sheet. Specific terms remain subject to confidential commercial agreements.

TSMC has not issued a regulatory filing on the Taiwan Stock Exchange or the U.S. Securities and Exchange Commission, and the company declined to confirm specific contract terms.

The company maintains that its pricing strategy remains strategic rather than opportunistic. Formal customer negotiations over 2027 allocations conclude during annual volume commitment reviews in late 2026.

The revised wafer-out price structure takes effect on Jan. 1, 2027, across all confirmed purchase orders.