MediaTek hires Intel packaging veteran for dual foundry push

MediaTek consolidated its dual advanced packaging strategy on Nov. 6, 2026, preparing for former Intel manufacturing executive Navid Shahriari to take office as senior vice president under an expanded multi-foundry architecture.

The company announced the executive appointment on Nov. 4, scheduling his formal start for Nov. 9. Shahriari spent 37 years at Intel, directing wafer fabrication, product engineering and back-end chiplet packaging operations.

Shahriari will report directly to Joe Chen, MediaTek's president and chief operating officer. His operational scope covers advanced manufacturing processes, design-technology co-optimization, testing, packaging and product reliability platforms.

The appointment underpins MediaTek's push into data center custom silicon. The company targets $2.5 billion in quarterly artificial intelligence revenue and a 20% share of the cloud accelerator market by 2027.

Advanced packaging has emerged as the central operational constraint for data center accelerators. High-bandwidth memory integration requires dense physical interconnects, forcing chip designers to secure guaranteed packaging capacity alongside raw front-end wafer fabrication.

MediaTek confirmed its dual packaging framework in August, when Chief Executive Officer Rick Tsai said the company would utilize both Taiwan Semiconductor Manufacturing Co. and Intel Foundry for artificial intelligence applications.

TSMC provides Chip-on-Wafer-on-Substrate — known as CoWoS — which places compute dies and memory stacks onto a specialized silicon interposer. CoWoS remains the primary packaging standard for leading graphics processors and accelerators.

Intel provides Embedded Multi-die Interconnect Bridge, or EMIB, which embeds miniature silicon bridges within an organic substrate instead of using a full-sized interposer. The variant known as EMIB-T incorporates through-silicon vias to support vertical power and signal routing.

By adding EMIB-T to its product roadmap, MediaTek secures secondary back-end assembly lines outside TSMC. The dual framework allows the design house to protect delivery schedules against allocation caps at Taiwanese packaging sites.

The dual structure also reflects technical preferences among hyperscale cloud clients. Analysts link MediaTek's initial EMIB-T deployment to custom tensor processing units designed for Google, where package substrate dimensions favor bridge-based interconnects.

Google sought alternative packaging options due to interposer size limitations and tight allocations at TSMC, according to industry sources. U.S. cloud providers have also requested geographically diversified assembly lines to insulate server deployment schedules.

MediaTek has systematically assembled senior engineering talent from both manufacturing camps. In May 2026, the company recruited Douglas Yu, former TSMC vice president of research and development and a lead developer of CoWoS, as a technical advisor.

Yu oversaw the commercial rollout of wafer-level packaging during his tenure at TSMC. His advisory role helped MediaTek establish its internal back-end integration roadmap for multi-die server architectures.

Shahriari complements that expertise with direct oversight of Intel's proprietary packaging lines. During his career at Intel, Shahriari managed back-end factory ramp-ups and yield optimization across advanced microarchitectures.

MediaTek said Shahriari will deepen collaboration with key foundry partners, explicitly naming TSMC in its recruitment announcement. The phrasing indicates that hiring an Intel veteran is not intended to displace MediaTek's primary foundry supplier.

TSMC manufactures the vast majority of MediaTek's mobile application processors and network silicon. Maintaining close operational coordination with TSMC remains essential for MediaTek's 3-nanometer and 2-nanometer product generations.

Deploying two packaging technologies simultaneously introduces complex test and yield variables. Bridge-based architectures require distinct substrate design rules and thermal dissipation profiles compared to interposer-based modules.

Shahriari's group will coordinate directly with foundry partners to establish design-technology co-optimization standards. That coordination aims to shorten cycle times for high-complexity multi-die chip assemblies.

The strategy allows MediaTek to challenge established application-specific integrated circuit vendors. Broadcom and Marvell Technology currently control the majority of custom cloud accelerator designs.

Securing dual packaging capability gives MediaTek a distinct commercial pitch for cloud service providers seeking guaranteed production capacity. Cloud operators require firm commitments that packaging bottlenecks will not delay server cluster deployments.

Shahriari formally begins his responsibilities at MediaTek's Hsinchu headquarters on Nov. 9, 2026. His initial operational focus will center on qualification pipelines for next-generation data center accelerators.

MediaTek's official announcement does not disclose contracted packaging volume splits between TSMC and Intel, and neither company has published commercial shipment timelines for EMIB-T accelerator products.