JCET expands automotive radar SiP packaging lines to capture ADAS sensor demand

JCET Group, China's largest outsourced semiconductor assembly and test provider, has commissioned dedicated high-density system-in-package manufacturing lines for automotive millimeter-wave radar modules at its primary production base in Jiangyin, Jiangsu province. The expansion targets 77-gigahertz and 79-gigahertz radar transceivers used in advanced driver-assistance systems, moving the company deeper into high-reliability automotive electronics packaging.

The Jiangsu-based packaging firm ranks third globally in outsourced semiconductor assembly and test revenue behind Taiwan's ASE Technology Holding and United States-headquartered Amkor Technology. Automotive radar packaging has emerged as a high-margin growth segment as passenger vehicles integrate multiple radar units for adaptive cruise control, autonomous emergency braking, and blind-spot detection. Transitioning from discrete surface-mount components to highly integrated System-in-Package (SiP) and Antenna-in-Package (AiP) architectures allows Tier-1 automotive suppliers to shrink sensor footprints while cutting electromagnetic interference at high radio frequencies.

JCET's newly commissioned lines utilize multi-layer fine-pitch redistribution layers, copper pillar flip-chip interconnects, and double-sided molded ball grid array architectures. The packaging flow integrates high-frequency radio-frequency complementary metal-oxide-semiconductor (RF-CMOS) or silicon-germanium (SiGe) transceiver monolithic microwave integrated circuits (MMICs) alongside dedicated digital signal processors, power management integrated circuits, and passive discrete components within a single encapsulated module. The company has also integrated compartmental physical vapor deposition electromagnetic interference shielding directly onto the epoxy mold compound, eliminating external metal shields that add assembly mass and thickness.

Automotive radar modules operate under severe thermal and vibrational stress, requiring packaging lines to meet automotive qualification standards before mass commercial delivery. JCET's expanded Jiangyin lines are certified under the AEC-Q100 Grade 1 and Grade 0 stress test qualification requirements, operating within ambient temperature windows spanning minus 40 degrees Celsius to 150 degrees Celsius. The manufacturing lines also operate in compliance with ISO 26262 functional safety standards up to Automotive Safety Integrity Level D (ASIL-D), addressing strict thermal dissipation and board-level solder joint reliability constraints.

The capacity expansion directly impacts the procurement strategy of domestic Chinese automotive radar designers and global Tier-1 system integrators. Chinese fabless automotive radar chip design firms, including Calterah Semiconductor and Silicon Radar, rely on regional OSAT capacity to assemble radar front-end integrated circuits for domestic electric vehicle makers such as BYD, Geely Automobile Holdings, and Chery Automobile. Global automotive semiconductor suppliers, including NXP Semiconductors, Infineon Technologies, and Texas Instruments, have traditionally routed advanced automotive radio-frequency packaging through packaging facilities in Taiwan, Malaysia, and the Philippines.

JCET is positioning its expanded SiP lines to secure dual-sourcing contracts from international Tier-1 automotive electronics suppliers operating production facilities inside China, such as Bosch, Continental, and Desay SV. Integrating multi-channel radar transceivers and planar patch antennas into compact AiP configurations reduces high-frequency transmission line losses between the antenna and the transceiver die. High-frequency millimeter-wave signals at 77 gigahertz suffer acute signal attenuation over standard printed circuit board traces; encapsulating antenna elements directly above or beside the transceiver substrate minimizes insertion loss and broadens the field of view for forward-looking and corner radar assemblies.

The investment reflects a broader shift by leading Chinese packaging vendors toward advanced packaging to offset restrictions on advanced front-end wafer fabrication equipment. Advanced packaging technologies such as flip-chip ball grid arrays, embedded wafer-level ball grid arrays, and high-density SiP enable system performance gains through heterogeneous integration without requiring sub-7-nanometer lithography tools. JCET allocated 3.1 billion yuan ($430 million) in capital expenditure during the first half of 2026, directing the largest share of equipment spending toward high-density packaging and automated test equipment for automotive and high-performance computing chips.

Upstream materials and precision equipment suppliers are seeing immediate order allocation from the Jiangyin facility expansion. The production lines consume high-frequency, low-loss substrate materials with low dielectric constants and dissipation factors, supplied by specialized laminators such as Shengyi Technology and Japan's Resonac Holdings. Precision wire bonders, ultra-thin wafer grinders, and automatic optical inspection machines have been installed from equipment suppliers including DISCO Corporation and Besi.

Domestic vehicle manufacturers in China are increasing standard radar fitment from one forward-facing unit to five-unit arrays per vehicle across mid-tier vehicle trims. High-density SiP packaging reduces the total bill of materials for sensor modules by eliminating auxiliary discrete printed circuit boards and secondary radio-frequency shielding hardware. By lowering unit packaging overhead and thermal resistance, JCET aims to capture a larger share of the automotive radar market as domestic automaker production schedules ramp through the second half of 2026.

JCET has begun initial commercial engineering sample shipments of the new SiP modules to automotive radar Tier-1 customers, with full-scale high-volume manufacturing scheduled to phase into serial production through the fourth quarter of 2026.