# TSMC secures $30,000 wafer rate, while Rapidus slips on 2nm ramp *A 50% price jump over 3-nanometer contracts cements TSMC's 72.5% market share as the Japanese contender pushes Chitose commercial volume to early 2028.* **Published:** November 15, 2026 **By:** Mina Okoro **Section:** Semiconductors & AI Hardware — Cross-border **Format:** Why It Matters **Confidence:** high **Source:** https://eastasiabrief.com/semiconductors/tsmc-secures-30-000-wafer-rate-while-rapidus-slips-1448 **Publisher:** East Asia Brief (https://eastasiabrief.com/) --- ## What to know - TSMC sets 2nm wafer contract rates at $30,000 as challengers miss yield milestones - Rapidus confirms delayed static random access memory bitcell validation at Chitose pilot line - Big tech buyers delay secondary sourcing while TSMC maintains a 72.5% foundry revenue share ![A technician in cleanroom attire observes a silicon wafer moving along an automated track inside a semiconductor fabrication facility. (AI-generated image)](https://eastasiabrief.com/media/2026-11-15-3abab9c6f620.webp) *A technician in cleanroom attire observes a silicon wafer moving along an automated track inside a semiconductor fabrication facility. (AI-generated image)* Rapidus reaffirmed on Nov. 14, 2026, that it is targeting commercial 2-nanometer wafer output by early 2028, confronting delays in proving memory bitcells at its Chitose pilot facility. Taiwan Semiconductor Manufacturing Co. currently prices 2-nanometer production at $30,000 per 300-millimeter wafer. That contract rate represents a 50% increase over the $20,000 baseline charged for 3-nanometer wafers. TSMC commanded 72.5% of global wafer foundry revenue in the second quarter of 2026, setting a record high. The single-node price hike directly inflates production overhead across the artificial intelligence hardware supply chain. Hyperscale data-center operators and chip designers have actively pursued second-sourcing strategies to dilute single-foundry dependence. Securing secondary suppliers would typically restore bargaining power in wafer procurement talks, but viable leading-edge alternatives remain scarce. Apple holds the earliest reservations for TSMC's 2-nanometer capacity, committing to take approximately half of initial fab runs for next-generation mobile processors. The consumer giant budgets around the higher wafer price to secure manufacturing priority. Nvidia and AMD face equivalent cost floors for their next-generation data-center computing silicon. Both chip designers fabricate their flagship artificial intelligence accelerators at TSMC without the margin relief that dual-sourcing contracts usually supply. Rapidus intended to enter high-volume manufacturing by March 2028 at its Innovative Integration for Manufacturing fab, known as IIM-1, in Hokkaido. The Japanese startup broke ground on the fab in September 2023. Engineers at Chitose installed extreme ultraviolet lithography machinery in late 2024 and began pilot wafer exposure on April 1, 2025. The company verified operation of individual 2-nanometer gate-all-around transistors in July 2025. The foundry ran into difficulties validating static random access memory bitcells during the summer of 2026, slipping behind internal development targets. These micro-scale memory circuits serve as essential cache storage inside high-performance computing logic chips. Without functioning SRAM arrays to hold temporary calculations, fabricators cannot progress from single-transistor proofs to viable multi-core processors. Particulate contamination inside the Chitose cleanrooms contributed to the development delays, Rapidus reported in technical reviews. Japan's government has backed Rapidus as the centerpiece of its industrial reconstruction policy. The New Energy and Industrial Technology Development Organization approved ¥1.72 trillion ($11.2 billion) in commissioned research budgets for the venture through fiscal 2025. State-controlled Information Technology Promotion Agency provided ¥100 billion alongside ¥167.6 billion from 32 domestic corporations in February 2026. That combined ¥267.6 billion equity injection funded cleanroom buildouts and front-end equipment acquisitions. A delay of several quarters shortens the foundry's commercial runway. Rapidus launched its CORE partner network in October 2026 with 17 design service vendors, including Synopsys and Infosys, to attract fabless design commitments. Intel Foundry has similarly struggled to turn leading-edge process announcements into third-party commercial contracts. The American chipmaker terminated its 20A development line in 2024 to consolidate capital around its 18A and enhanced 18A-P nodes. Intel produces about 30,000 wafers per month across Fab 52 in Arizona and developmental lines in Oregon. Internal assembly lines consume nearly that entire volume to build the company's proprietary Panther Lake personal computer processors. The company initiated risk production of its 18A-P node in June 2026 at the VLSI Symposium in Honolulu. Risk production allows foundries to fabricate initial test silicon under commercial conditions before committing to full production lines. The 18A-P variant yields 9% higher computing speed or 18% lower electricity consumption compared to the baseline node, Intel said. However, Intel has yet to finalize a binding volume manufacturing deal with an external fabless customer. Samsung Electronics also contends with yield consistency hurdles across its gate-all-around 2-nanometer offering, designated SF2. The South Korean manufacturer has not converted external pilot tests into long-term volume purchase contracts for advanced mobile chipsets. The technical barriers across rival pilot fabs keep leading-edge pricing power firmly with TSMC. Fabless chip designers must accept non-negotiable wafer prices or postpone their node transitions by a full generation. The Ministry of Economy, Trade and Industry convenes its next semiconductor project review in December 2026 to evaluate a planned ¥400 billion equity injection for Rapidus. The ministry has not published verified wafer defect densities or defect per square centimeter data for the Chitose pilot line, leaving yield rates unconfirmed. TSMC plans to begin commercial customer deliveries from its 2-nanometer production lines in the first half of 2027. ## Impact map | Event | Korea | China | Japan | Global impact | | --- | --- | --- | --- | --- | | Leading-edge 2nm foundry pricing power | Samsung Foundry faces commercial pressure to secure external volume commitments for SF2 | Domestic fabricators remain restricted from purchasing leading-edge extreme ultraviolet systems | Rapidus absorbs ¥1.72 trillion in research subsidies while deferring mass production to 2028 | Hyperscale chip buyers absorb a 50% wafer price jump to $30,000 without second-source leverage | ## In this story - **Companies:** Taiwan Semiconductor Manufacturing Co., Rapidus, Intel - **Tickers:** 2330.TW, INTC - **Exposed:** Apple, Nvidia, AMD, Samsung Electronics - **Policy:** Subsidies - **Impact:** Pricing, Supply Chain, Capex ## Primary sources 1. meti.go.jp 2. japantimes.co.jp 3. monoscope-media.com 4. zdnet.co.kr 5. mk.co.kr --- Cite as: East Asia Brief, "TSMC secures $30,000 wafer rate, while Rapidus slips on 2nm ramp," November 15, 2026. https://eastasiabrief.com/semiconductors/tsmc-secures-30-000-wafer-rate-while-rapidus-slips-1448