# SK hynix unveils MARS rack architecture to break HBM limits *The disaggregated memory system and flash tier target agentic AI workloads, delivering up to 14 times the density of conventional stacked DRAM.* **Published:** October 14, 2026 **By:** Ji-woo Han **Section:** Semiconductors & AI Hardware — South Korea **Format:** Breaking **Confidence:** medium **Source:** https://eastasiabrief.com/semiconductors/sk-hynix-unveils-mars-rack-architecture-break-hbm-limits-708 **Publisher:** East Asia Brief (https://eastasiabrief.com/) --- ## What to know - MARS rack pool cuts inference latency by 3.5x to 5.2x - HBF flash delivers 14x density over stacked DRAM up to 512GB - Specification 1.0 arrives in January 2027 before 2028 sampling ![Engineers in lab coats inspect illuminated server racks inside a data center while reviewing AI memory hardware systems. (AI-generated image)](https://eastasiabrief.com/media/2026-10-14-86689f9acf34.webp) *Engineers in lab coats inspect illuminated server racks inside a data center while reviewing AI memory hardware systems. (AI-generated image)* SK hynix introduced its Memory-Centric AI Rack System architecture on Oct. 13, 2026, deploying disaggregated server memory pools to bypass physical density bottlenecks in conventional high-bandwidth memory stacks. The technical disclosure took place during the Open Compute Project Global Summit in San Jose, California. The design addresses severe thermal and capacity ceilings encountered in accelerator clusters, the company said. Benchmark tests showed the pooled architecture cuts time-to-first-token latency by 3.5 to 5.2 times during multi-turn agentic inference. The system stores conversational context without exhausting accelerator memory, the company said. Traditional server architecture couples memory directly to host processors, forcing operators to purchase redundant graphics chips simply to expand storage capacity. This structural mismatch inflates cluster operating expenses across commercial data centers. The MARS platform pools memory across dedicated trays through Compute Express Link interfaces. Multiple computing nodes access this shared capacity simultaneously without copying large data tables across network fabrics. This design enables zero-copy sharing for key-value caches during complex artificial intelligence queries. The caching mechanism maintains conversational context in shared memory rather than consuming scarce high-bandwidth memory on accelerator boards. SK hynix holds roughly 53% of the global market for high-bandwidth memory. The supplier seeks alternative packaging tiers as physical thermal constraints limit how many memory dies fabricators can stack vertically. Standard memory packaging encounters structural limits when stacking silicon beyond 16 layers. Microscopic copper connections risk thermal distortion and mechanical failure under sustained operating heat inside dense accelerator modules. The company also detailed its High Bandwidth Flash roadmap alongside the rack architecture. The flash standard delivers roughly 14 times the storage density of existing stacked dynamic random-access memory. The storage specification stacks non-volatile NAND flash vertically in eight-layer and 16-layer configurations. Package capacities reach up to 512 gigabytes while consuming approximately 60% less electrical power than DRAM stacks. Data bandwidth reaches 3.0 terabytes per second across the highest performance tier. That throughput matches roughly half the speed of comparable high-bandwidth memory while slashing component fabrication costs. The flash package connects directly to processors through Universal Chiplet Interconnect Express physical interfaces. This standard allows systems builders to place dense flash memory directly onto multi-chip packaging substrates alongside logic silicon. Ahn Hyun, chief development officer at SK hynix, affirmed the product roadmap during an industry address in Seoul on Oct. 14, 2026. The company intends to resolve persistent inference memory bottlenecks, Ahn said. Ahn explained that 3D stacked dynamic random-access memory will eventually sit directly on top of neural processing units. The three-dimensional stacking technique removes horizontal wiring delays between logic circuits and memory arrays. SanDisk co-developed the initial standard specifications for the high-bandwidth flash format under an open-industry working group. The flash maker oversees interface specifications aimed at mass-market enterprise solid-state drives. Google and processor startup Tenstorrent participate in the consortium developing the memory interface. The enterprise buyers require denser memory tiers to handle multi-modal language models spanning billions of parameters. Hyperscale operators currently spend up to 70% of server power budgets on data transfers between processors and memory. Disaggregated pools reduce these transmission losses by staging active data nearer to compute resources. By separating processing hardware from memory banks, cloud facilities can scale storage capacity independently. Operators avoid purchasing additional computing nodes merely to satisfy working memory requirements. The architecture directly challenges traditional packaging systems designed by server assemblers. Taiwanese contract manufacturers must redesign rack backplanes to accommodate optical interconnects and high-speed switching fabrics demanded by pooled systems. Foundries and assembly providers also face shifts in thermal packaging parameters. Stacking flash memory near processing logic requires advanced heat dissipation materials to prevent thermal throttling under continuous inference workloads. Consortium members plan to finalize the formal 1.0 high-bandwidth flash specification in January 2027 before distributing engineering samples to customers in early 2028. The company has not published a standalone regulatory filing or official newsroom release detailing commercial licensing terms for the MARS platform. Samsung Electronics and Micron Technology continue developing competing disaggregated memory modules. Both rivals have demonstrated prototype expansion cards using similar peripheral component interconnect standards. Commercial deployment of pooled rack systems remains contingent on broad industry adoption of third-generation interconnect switches. Server fabricators must qualify high-speed physical layers before hyper-scale data centers can reconfigure existing installations. SK hynix demonstrated operating rack hardware to summit attendees at the San Jose Convention Center. Technical working groups within the open compute foundation received preliminary hardware design guides following the address. ## Impact map | Event | Korea | China | Japan | Global impact | | --- | --- | --- | --- | --- | | MARS and HBF memory architecture disclosure | SK hynix expands portfolio beyond HBM to defend 53% market position against Samsung | Hyperscale operators face delayed access if advanced CXL interfaces fall under export limits | SanDisk standardizes joint flash packaging while materials suppliers adjust thermal layers | Data center operators cut GPU over-provisioning capex by pooling agentic memory | ## In this story - **Companies:** SK hynix - **Tickers:** 000660.KS - **Exposed:** Google, Tenstorrent, Samsung Electronics, Micron Technology - **Policy:** Economic Security - **Impact:** Supply Chain, Capex, Cost Structure ## Primary sources 1. zdnet.co.kr 2. press9.kr 3. hankyung.com 4. businesskorea.co.kr 5. trendforce.com --- Cite as: East Asia Brief, "SK hynix unveils MARS rack architecture to break HBM limits," October 14, 2026. https://eastasiabrief.com/semiconductors/sk-hynix-unveils-mars-rack-architecture-break-hbm-limits-708