# Rapidus taps India's HCLTech for 2nm logic chip design work
*The Japanese foundry launched two dedicated engineering centers in Bengaluru and Hubli to offset domestic engineer shortages ahead of mass production in fiscal 2027.*
**Published:** November 1, 2026
**By:** Kenji Sato
**Section:** Semiconductors & AI Hardware — Japan
**Format:** Breaking
**Confidence:** medium
**Source:** https://eastasiabrief.com/semiconductors/rapidus-taps-india-s-hcltech-2nm-logic-chip-design-1039
**Publisher:** East Asia Brief (https://eastasiabrief.com/)
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## What to know
- Rapidus opened two chip design centers with HCLTech in Bengaluru and Hubli on Oct. 26
- HCLTech logged $14.8 billion in trailing revenue, though partnership contract value is unstated
- Rapidus targets initial PDK release in fiscal 2026 and 2nm mass production in fiscal 2027
*Engineers wearing cleanroom suits inspect semiconductor manufacturing equipment while consulting a digital tablet. (AI-generated image)*
Rapidus and HCL Technologies formalized an engineering partnership on Oct. 26, 2026, expanding joint design work through Oct. 30 to support Japan's 2-nanometer logic chips.
The agreement establishes two development centers in Bengaluru and Hubli to support chip manufacturing at Rapidus. HCL Technologies generated $14.8 billion in consolidated revenue over the 12 months ended Sept. 30, 2026.
Neither company disclosed the contract value or capital expenditure allocated to the two centers. The partners also withheld the specific number of engineers assigned to the facilities, according to exchange filings in Mumbai.
Rapidus Chief Executive Officer Atsuyoshi Koike and HCL Technologies Chief Executive Officer C Vijayakumar signed the agreement at HCLTech headquarters in Noida. Both centers began immediate commercial operations the same day.
The facilities will build process design kits — the software packages containing design rules and simulation models for manufacturing. Rapidus plans to release the kits during fiscal 2026 to prospective semiconductor customers.
Engineers at the sites will also handle design technology co-optimization — the simultaneous tuning of circuit layout and fabrication steps. The process reduces defect rates before silicon runs begin in Japan.
The scope spans mask design, design infrastructure and physical layout design. These operations verify that electronic circuits translate accurately onto optical masks used in extreme ultraviolet lithography tools.
Japan faces a structural deficit of semiconductor design talent after three decades of foundry market share losses. Domestic universities produce fewer specialized device engineers than needed for cutting-edge logic production.
The partnership establishes a talent pipeline to recruit and train Indian engineering graduates. Selected engineers will relocate to Japan to augment the technical workforce at Rapidus facilities, Koike said.
The agreement follows the launch of Rapidus CORE on Oct. 5, 2026. Rapidus established that framework with 17 initial design partners to assemble an intellectual property and design service network.
HCL Technologies joined the program as an official Design Solution Alliance partner. The Indian IT company maintains similar design partnerships with Taiwan Semiconductor Manufacturing Co., Samsung Electronics and Intel.
HCL Technologies has completed more than 230 tape-outs across global foundries. It also operates a 40,000-square-foot testing and silicon validation cleanroom facility at its primary campus in Bengaluru.
Foundries require mature design service networks so fabless customers can port chip architectures without delays. Without third-party design houses, fabless clients cannot access proprietary manufacturing recipes at reasonable cost.
Rapidus operates under a specialized model designed to shorten production cycle times for custom artificial intelligence processors. That approach requires fast translation from customer architectural files into ready masks.
Hubli was selected alongside Bengaluru to tap engineering talent emerging outside India's primary tech hubs. The two centers run on synchronized networks to mirror Tokyo operational hours.
Rapidus is constructing its initial fabrication facility, Innovative Integration for Manufacturing, in Chitose, Hokkaido. The company aims to begin commercial mass production of 2-nanometer logic chips in fiscal 2027.
IBM Japan opened a dedicated technical office in Chitose on Oct. 26 to assist local operations. IBM licensed the baseline 2-nanometer nanosheet transistor architecture to Rapidus under a 2022 bilateral research pact.
The Japanese government has approved 920 billion yen ($6 billion) in subsidies for Rapidus through the Ministry of Economy, Trade and Industry. The subsidies fund cleanroom construction and equipment installation in Hokkaido.
India has sought closer semiconductor ties with Japan under bilateral supply chain agreements signed in 2023. The Indian government promotes domestic chip design while Japanese foundries supply advanced manufacturing capacity.
The regulatory filings do not state the financial value of the contract, the capital expenditure allocated to the two centers, or the total headcount committed to the talent pipeline.
Rapidus plans to distribute its 2-nanometer process design kits to select customers in fiscal 2026. Commercial wafer output remains scheduled to commence in Chitose during fiscal 2027.
## Impact map
| Event | Korea | China | Japan | Global impact |
| --- | --- | --- | --- | --- |
| Rapidus-HCLTech engineering alliance | Samsung foundry faces expanded design service competition for fabless customers | CXMT and SMIC remain isolated from leading-edge Indian engineering services | Rapidus closes design talent deficit ahead of Chitose 2nm ramp in fiscal 2027 | Fabless AI chipmakers gain design bridge to alternative Japanese 2nm foundry |
| Rapidus-HCLTech engineering alliance | Samsung foundry faces expanded design service competition for fabless customers | CXMT and SMIC remain isolated from leading-edge Indian engineering services | Rapidus closes design talent deficit ahead of Chitose 2nm ramp in fiscal 2027 | Fabless AI chipmakers gain design bridge to alternative Japanese 2nm foundry |
## In this story
- **Companies:** Rapidus, HCL Technologies
- **Tickers:** 532281.BO, HCLTECH.NS
- **Exposed:** IBM
- **Policy:** Subsidies
- **Impact:** Supply Chain, Capex, Order Book
## Primary sources
1. japantimes.co.jp
2. hcltech.com
3. rapidus.inc
4. dempa.net
5. bseindia.com
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Cite as: East Asia Brief, "Rapidus taps India's HCLTech for 2nm logic chip design work," November 1, 2026. https://eastasiabrief.com/semiconductors/rapidus-taps-india-s-hcltech-2nm-logic-chip-design-1039