# Montage and Panmnesia validate CXL 3.1 memory silicon with Samsung and SK hynix *East Asian chip designers and memory manufacturers begin sampling PCIe 6.2 controllers and switches to scale AI server memory bandwidth and reduce total cost of ownership.* **Published:** August 29, 2026 **By:** Mina Okoro **Section:** Semiconductors & AI Hardware — Cross-border **Format:** Why It Matters **Confidence:** medium **Source:** https://eastasiabrief.com/semiconductors/montage-panmnesia-validate-cxl-3-1-memory-silicon-samsung-109 **Publisher:** East Asia Brief (https://eastasiabrief.com/) --- ## What to know - Montage Technology and fabless designer Panmnesia have commenced customer-level silicon validation for their Compute Express Link 3. - The validation cycle marks a decisive technical shift in East Asia's semiconductor supply chain from first-generation CXL 2. - Montage Technology has distributed initial engineering samples of its M88MX6852 memory expander controller, a Type 3 device engineered around a native PCIe 6. ![Engineers inspect a semiconductor component in a testing laboratory surrounded by electronic circuit boards and diagnostic displays. (AI-generated image)](https://eastasiabrief.com/media/2026-08-28-20b3f233e401.webp) *Engineers inspect a semiconductor component in a testing laboratory surrounded by electronic circuit boards and diagnostic displays. (AI-generated image)* Montage Technology and fabless designer Panmnesia have commenced customer-level silicon validation for their Compute Express Link 3.1 memory expander controllers and switch chipsets, initiating multi-host interoperability trials with Samsung Electronics and SK hynix to resolve server memory bandwidth bottlenecks in artificial intelligence infrastructure. The validation cycle marks a decisive technical shift in East Asia's semiconductor supply chain from first-generation CXL 2.0 silicon toward the PCIe 6.2 physical layer, doubling line rates from 32 gigatransfers per second to 64 gigatransfers per second. For global cloud service providers operating dense accelerator clusters, the transition targets stranded DRAM capacity and interconnect latency that degrade the total cost of ownership in large language model inference workloads. Montage Technology has distributed initial engineering samples of its M88MX6852 memory expander controller, a Type 3 device engineered around a native PCIe 6.2 physical layer that supports full x8 link widths or dual x4 subdivisions. The controller integrates dual-channel DDR5 physical interfaces capable of data rates up to 8000 megatransfers per second, interfacing host processors directly with discrete DRAM arrays across standard EDSFF E3.S module enclosures and half-height half-length PCIe add-in cards housed in a 25-millimeter by 25-millimeter ball grid array package. To manage real-time traffic arbitration and fabric isolation within disaggregated server chassis, the M88MX6852 incorporates dual embedded RISC-V microprocessors designated as an Application Processing Unit and a Security Processing Unit. These execution blocks govern dynamic memory resource allocation, process system health telemetry over SMBus and I3C telemetry interfaces, and enforce hardware-level Trusted Security Protocol specifications required by multi-tenant cloud data center architectures. The memory expansion architecture relies on the concurrent operation of CXL.io for device configuration and CXL.mem for direct, low-latency memory transactions over load-store semantics. By bypassing operating system storage stacks and standard block device drivers, the Type 3 memory controller allows server central processing units and attached accelerators to treat expansion modules as native byte-addressable system memory with near-zero software overhead. Complementing endpoint expansion controllers, South Korean intellectual property designer Panmnesia has finalized silicon tape-out and interoperability demonstrations for its CXL 3.1 fabric switch architecture. The switch silicon facilitates non-blocking multi-logical device configurations, allowing multiple host processors and graphical processing units to dynamically map shared memory pools across port-based routing and hierarchy-based routing topographies without incurring operating system kernel overhead. Under the CXL 3.1 specification, the introduction of advanced fabric switching enables scale-out topologies where dozens of heterogeneous compute nodes attach to a centralized memory drawer. Hardware-enforced back-invalidation mechanisms maintain cache coherency across interconnected compute nodes, preventing data inconsistencies when multiple server blades concurrently read and write to the same physical memory regions. Samsung Electronics has aligned its memory module engineering with the emerging controller ecosystem, advancing validation for its CXL Memory Module DRAM platform across server motherboards and chassis backplanes. The manufacturer’s CMM-D hardware supports capacities reaching 1 terabyte per module and sustains data throughput of 72 gigabytes per second, enabling infrastructure operators to scale server memory capacity independently from fixed motherboard dual in-line memory module socket limitations. SK hynix has integrated its CMM-DDR5 module hardware with the proprietary Heterogeneous Memory Software Development Kit, designated HMSDK, which coordinates physical page placement between high-bandwidth memory, standard host DDR5 channels, and pooled CXL memory devices. In benchmark trials evaluating disaggregated caching and in-memory key-value databases, the integrated software stack reduced performance degradation to 6 percent compared with standard direct-attached DRAM configurations, outperforming legacy non-uniform memory access rebalancing routines. Transitioning from CXL 2.0 to CXL 3.1 introduces signal integrity challenges across physical server backplanes due to the adoption of four-level pulse amplitude modulation signaling at 64 gigatransfers per second. Because high-frequency attenuation halves channel reach compared with non-return-to-zero PCIe 5.0 signaling, board integrators are validating dedicated PCIe 6.2 retimer integrated circuits and low-loss PCB dielectric substrates to maintain clean eye diagrams across multi-slot server drawers. Testing and characterization requirements have shifted simultaneously across backend test facilities in South Korea and China, as standard automated test equipment designed for legacy DDR5 memory cannot validate the bidirectional high-speed serial protocols of PCIe 6.2 interfaces. Specialized CXL test fixtures must now verify packet error rates, forward error correction performance, link training state machines, and thermal throttling under continuous 25-watt envelope conditions within E3.S form factor enclosures. Commercial server deployments throughout 2026 continue to center on production-qualified CXL 2.0 memory modules, with CXL 3.1 controller silicon and switch architectures remaining in rigorous customer sampling and electrical characterization phases. The qualification timeline aligns with incoming host server processor platforms from Intel and Advanced Micro Devices, with data center operators conducting firmware level stress tests across multi-vendor memory expander cards. ## Impact map | Event | Korea | China | Japan | Global impact | | --- | --- | --- | --- | --- | | CXL 3.1 validation | module and switch validation | controller IC sampling | test and material supply | AI server memory pooling | ## In this story - **Companies:** Montage Technology, Panmnesia, Samsung Electronics, SK hynix - **Tickers:** 688008.SS, 005930.KS, 000660.KS - **Exposed:** Intel, AMD, NVIDIA - **Policy:** Economic Security, Subsidies - **Impact:** Supply Chain, Capex, Cost Structure ## Primary sources 1. stockplus.com 2. newswire.co.kr 3. efactorynews.com 4. businesskorea.co.kr 5. newstheai.com --- Cite as: East Asia Brief, "Montage and Panmnesia validate CXL 3.1 memory silicon with Samsung and SK hynix," August 29, 2026. https://eastasiabrief.com/semiconductors/montage-panmnesia-validate-cxl-3-1-memory-silicon-samsung-109