# Korean tool makers advance high-k ALD platforms for sub-10nm 3D DRAM fabs *State-backed R&D programs and fab equipment vendors target ultra-thin capacitor films with dielectric constants above 100 for next-generation memory architectures.* **Published:** September 1, 2026 **By:** Ji-woo Han **Section:** Semiconductors & AI Hardware — South Korea **Format:** Why It Matters **Confidence:** medium **Source:** https://eastasiabrief.com/semiconductors/korean-tool-makers-advance-high-k-ald-platforms-sub-144 **Publisher:** East Asia Brief (https://eastasiabrief.com/) --- ## What to know - South Korea's Ministry of Science and ICT allocated funding on Aug. - Equivalent oxide thickness measures how thin a silicon dioxide layer would need to be to achieve the same capacitance as a given high-k dielectric material. - Conventional planar DRAM architectures face physical scaling barriers as process nodes shrink below 10 nanometers. ![Researchers in lab coats examine advanced semiconductor processing equipment during materials development in a laboratory. (AI-generated image)](https://eastasiabrief.com/media/2026-08-31-1b192ddf8ba8.webp) *Researchers in lab coats examine advanced semiconductor processing equipment during materials development in a laboratory. (AI-generated image)* South Korea's Ministry of Science and ICT allocated funding on Aug. 28, 2026, for a multicomponent high-k atomic layer deposition program designed for sub-10nm three-dimensional dynamic random-access memory. The initiative commits 6.75 billion won ($4.9 million) over 54 months under the Nano-Material Technology Development Project. It sets performance targets of a dielectric constant exceeding 100 and an equivalent oxide thickness below 0.3 nanometers. Equivalent oxide thickness measures how thin a silicon dioxide layer would need to be to achieve the same capacitance as a given high-k dielectric material. Lower values permit denser charge storage without triggering destructive leakage currents. Conventional planar DRAM architectures face physical scaling barriers as process nodes shrink below 10 nanometers. At the 1b and 1c nanometer nodes, capacitor aspect ratios exceed 50 to one, creating severe mechanical collapse risks and electron leakage through zirconium dioxide and hafnium dioxide dielectrics. Leading memory manufacturers are shifting engineering resources toward 3D DRAM architectures. The architecture reorients the capacitor and transistor from a vertical pillar into a horizontally stacked configuration, multiplying memory cell density on a single die without requiring aggressive lateral shrinkage. Horizontal stacking requires atomic layer deposition (ALD) systems capable of coating complex lateral trenches with uniform film composition. Conventional chemical vapor deposition cannot achieve the requisite step coverage across multi-layer horizontal channels. Eugene Technology completed development of a titanium nitride ALD tool on Aug. 4, 2026, aimed at sub-10nm DRAM capacitor electrode layers. The company moved the system into pattern wafer demonstration testing with domestic memory manufacturers. The titanium nitride tool forms the conductive counter-electrode that encases the high-k dielectric film inside the capacitor cavity. Uniform electrode thickness prevents work-function variation and reduces contact resistance across nanometer-scale memory cells. Wonik IPS operates its HyEta spatial ALD platform to address high aspect ratio gap-fill and dielectric deposition challenges in advanced memory fabs. The system uses physically separated reaction zones rather than sequential time purges to prevent gas-phase precursor mixing. The platform processes six wafers simultaneously in a mini-batch configuration at temperatures between 300 and 700 degrees Celsius. Wonik IPS qualifies the system for zirconium oxide and aluminum oxide thin-film deposition across DRAM and high-density 3D NAND lines. Jusung Engineering supplies time-space divided ALD systems for capacitor dielectric manufacturing at SK hynix. The company relies on its local space plasma hardware to deposit high-dielectric films at temperatures below 300 degrees Celsius, minimizing thermal budgets on processed wafers. The supplier captured 101.1 billion won ($73.3 million) in front-end wafer fab equipment order backlog by the third quarter of 2025. It is adapting its atomic layer growth technology to deposit multicomponent perovskite-phase dielectrics for horizontal 3D capacitor stacks. High-volume production of dedicated 3D DRAM ALD equipment remains tied to development timelines at Samsung Electronics, SK hynix and Micron Technology. Commercial memory production currently relies on 2D planar 1b and 1c nodes, while 3D DRAM tools remain confined to pilot research lines. Samsung Electronics and SK hynix operate internal 3D DRAM evaluation lines to benchmark channel materials, ferroelectric films and multi-component high-k dielectrics. Neither chipmaker has finalized high-volume manufacturing tool orders or committed to a commercial mass-production schedule. Domestic tool vendors face international competition from ASM International, Tokyo Electron and Lam Research in leading-edge deposition. ASM International and Tokyo Electron control significant market share in thermal and plasma-enhanced ALD tools deployed across Korean memory fabs. The government-backed high-k project aims to establish local supply chains for precursor chemical synthesis, delivery hardware and chamber design. Foreign chemical manufacturers currently supply the majority of specialized hafnium and zirconium precursors used in domestic high-volume fabs. Multicomponent high-k films require precise co-doping of rare earth and transition metals to stabilize crystalline phases with ultra-high dielectric constants. Process engineers must suppress grain boundaries that act as leakage paths while maintaining atomic-level thickness uniformity across thousands of stacked layers. Transitioning from cylindrical capacitors to 3D stacked cells increases the total number of ALD process cycles per wafer. Equipment throughput and chamber cleaning intervals determine whether horizontal cell integration achieves cost parity with advanced planar scaling. The Ministry of Science and ICT will review initial dielectric material test coupons from research consortium members in November 2026. Memory producers will continue qualification runs of titanium nitride and high-k ALD modules on test wafer lots through the first half of 2027. ## Impact map | Event | Korea | China | Japan | Global impact | | --- | --- | --- | --- | --- | | 3D DRAM ALD tooling | local equipment vendor pilot entry | memory fab access restricted | ALD precursor export exposure | sub-10nm DRAM architecture transition | ## In this story - **Companies:** Wonik IPS, Eugene Technology, Jusung Engineering, Samsung Electronics, SK hynix - **Tickers:** 240810.KS, 084370.KQ, 036930.KQ, 005930.KS, 006600.KS - **Exposed:** ASM International, Tokyo Electron, Lam Research, Micron Technology - **Policy:** Subsidies, Economic Security - **Impact:** Supply Chain, Capex, Order Book ## Primary sources 1. rndcircle.io 2. ips.co.kr 3. greened.kr 4. orangeboard.co.kr 5. jusung.com --- Cite as: East Asia Brief, "Korean tool makers advance high-k ALD platforms for sub-10nm 3D DRAM fabs," September 1, 2026. https://eastasiabrief.com/semiconductors/korean-tool-makers-advance-high-k-ald-platforms-sub-144