# China DRAM Makers Advance Proprietary Vertical Stacking to Counter HBM Export Curbs

*Domestic memory fabricators and packaging houses deploy customized TSV tools and hybrid bonding to build localized high-bandwidth architectures.*

**Published:** August 28, 2026  
**By:** Wei Zhang  
**Section:** Semiconductors & AI Hardware — China  
**Format:** Company Watch  

**Source:** https://eastasiabrief.com/semiconductors/china-dram-makers-advance-proprietary-vertical-stacking-counter-hbm-28  
**Publisher:** East Asia Brief (https://eastasiabrief.com/)

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## What to know

- ChangXin Memory Technologies, the country's primary DRAM manufacturer, is conducting engineering trials on multi-layer die stacks fabricated on its baseline 17-nanometer and 18-nanometer class nodes.
- The initiative relies on an expanding domestic ecosystem of front-end equipment builders and outsourced semiconductor assembly and test providers.
- The structural pivot reflects the mounting compute requirements of domestic artificial intelligence accelerator developers, such as Huawei Technologies' HiSilicon unit, Biren Technology, and Moore Threads.

![A technician in protective cleanroom attire holds a component next to processing equipment inside a semiconductor manufacturing laboratory. (AI-generated image)](https://eastasiabrief.com/media/2026-08-28-9c5c77f9030a.png)
*A technician in protective cleanroom attire holds a component next to processing equipment inside a semiconductor manufacturing laboratory. (AI-generated image)*

Chinese dynamic random-access memory fabricators have initiated qualification runs for domestically integrated vertical DRAM stacking architectures, deploying domestically sourced through-silicon via tooling and direct wafer-to-wafer bonding to assemble high-bandwidth memory structures. The technical validation marks a concerted push by mainland semiconductor consortiums to establish a self-reliant supply route for artificial intelligence memory subsystems, bypassing multilateral export controls that restrict mainland access to advanced lithography and high-density memory stacks.

ChangXin Memory Technologies, the country's primary DRAM manufacturer, is conducting engineering trials on multi-layer die stacks fabricated on its baseline 17-nanometer and 18-nanometer class nodes. Because export regulations enforced by the United States Department of Commerce limit the export of wafer fabrication equipment capable of producing DRAM with half-pitches below 18 nanometers, domestic engineering efforts have prioritized vertical integration over horizontal node shrinks. By stacking six to eight DRAM dies through dense vertical interconnect matrices, the fabricators seek to offset the lower per-die storage density of trailing nodes with increased input-output line parallelism.

The initiative relies on an expanding domestic ecosystem of front-end equipment builders and outsourced semiconductor assembly and test providers. Front-end etching and chemical vapor deposition steps required for through-silicon via (TSV) formation are being handled on tools supplied by Naura Technology Group and Piotech, while wet-processing and wafer-cleaning stages draw on systems from ACM Research Shanghai and Kingsemi. On the back-end assembly side, specialized packaging houses including JCET Group, Tongfu Microelectronics, and SJ Semiconductor have configured dedicated pilot lines for wafer-level packaging, wafer thinning, and high-precision micro-bump bonding.

The structural pivot reflects the mounting compute requirements of domestic artificial intelligence accelerator developers, such as Huawei Technologies' HiSilicon unit, Biren Technology, and Moore Threads. These design firms face stringent constraints on importing foreign-manufactured high-bandwidth memory modules, including HBM2e, HBM3, and HBM3e components manufactured by SK hynix, Samsung Electronics, and Micron Technology. Without access to cutting-edge overseas merchant HBM, domestic accelerator architectures require custom memory subsystems that can match aggregate interconnect bandwidth thresholds, even at the cost of larger silicon footprints and higher baseline power consumption.

Process flows under evaluation diverge from standard merchant HBM manufacturing sequences in several respects. Standard high-bandwidth memory stacks rely heavily on 1alpha-nanometer and 1beta-nanometer DRAM dies joined by thermo-compression bonding with non-conductive film, or advanced mass reflow molded underfill techniques. In contrast, Chinese pilot lines are running dual-track evaluations: one utilizing thermo-compression micro-bump bonding with domestic underfill formulations, and an exploratory track focusing on dielectric-to-dielectric hybrid bonding without intermediate micro-bumps.

The hybrid bonding architecture, often categorized under direct copper-to-copper fusion bonding, enables a tighter interconnect pitch below one micrometer. That tighter pitch allows engineers to dramatically increase the number of vertical communication channels between stacked dies. The practical consequence of this approach is that fabricators can achieve higher aggregate memory bandwidth on trailing-edge silicon by multiplying the total number of parallel data pathways, rather than running individual pathways at the higher clock frequencies typical of sub-14nm dies.

Engineering data from pilot testing indicate persistent trade-offs in yield and thermal dissipation. Stacking thicker DRAM dies manufactured on 17nm-class nodes increases the total height of an eight-die stack, requiring specialized wafer-thinning equipment to grind silicon substrates down to less than 40 micrometers without introducing edge cracks or mechanical warp. Furthermore, the higher operational voltage of trailing-edge DRAM circuits generates greater thermal loads within the multi-die package, necessitating thicker copper heat spreaders and higher-conductivity thermal interface materials to prevent thermal throttling during continuous AI training workloads.

Domestic packaging specialists have also encountered yield friction in high-aspect-ratio TSV etching. Creating uniform, defect-free vertical channels through multi-layer silicon requires precise plasma etching and barrier-layer deposition to prevent copper migration into the active silicon substrate. Industry yield rates on the exploratory domestic eight-layer stacks remain well below the 80 percent threshold typical of commercial tier-one HBM3 production lines, according to technical disclosures from domestic packaging forums.

To bridge these yield gaps, mainland research bodies, including the Institute of Microelectronics of the Chinese Academy of Sciences, have established joint development laboratories with domestic foundries. These laboratories focus specifically on automated optical inspection algorithms, acoustic micro-imaging for void detection in bonding layers, and customized test vehicles designed to identify defective dies prior to final vertical integration.

The domestic assembly effort alters procurement schedules across the mainland AI hardware sector. Rather than designing board layouts around standard JEDEC-compliant HBM form factors, domestic accelerator architects are increasingly tailoring their memory physical interfaces (PHY) to match proprietary pinouts and non-standard packaging dimensions developed by local packaging consortia. This architectural divergence isolates the domestic compute supply chain from global standard components while establishing an internal ecosystem centered on domestic foundry and packaging capacities.

Commercial ramp schedules indicate that initial low-volume runs of domestically stacked memory modules will support localized server accelerator deployments through the fourth quarter of 2026. Equipment deliveries for dedicated TSV etching, grinding, and bonding tools from domestic vendors are scheduled to continue across pilot lines in Hefei, Wuxi, and Shanghai throughout the first half of 2027.

## Impact map

| Event | Korea | China | Japan | Global impact |
| --- | --- | --- | --- | --- |
| Proprietary DRAM Stacking | tier-1 HBM isolation | domestic TSV integration | packaging material pull | bifurcated AI memory architecture |

## In this story

- **Companies:** ChangXin Memory Technologies, JCET Group, Naura Technology Group
- **Tickers:** 600584.SS, 002371.SZ
- **Exposed:** Huawei Technologies, Tongfu Microelectronics, Piotech, ACM Research Shanghai
- **Policy:** Export Controls, Economic Security
- **Impact:** Supply Chain, Capex, Cost Structure

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Cite as: East Asia Brief, "China DRAM Makers Advance Proprietary Vertical Stacking to Counter HBM Export Curbs," August 28, 2026. https://eastasiabrief.com/semiconductors/china-dram-makers-advance-proprietary-vertical-stacking-counter-hbm-28